1. Field of the Invention
The present invention relates to an organic EL drive circuit and an organic EL display device using the same and, in particular, the present invention relates to an improvement of an organic EL drive circuit having a column line (anode side drive line of an organic EL element) current drive circuit for generating a pin drive current of an organic EL panel by generating a current corresponding to an input digital value by means of a D/A converter circuit utilizing a current mirror circuit, such that a D/A converted current exceeding the number of converted bits can be obtained and an area of the organic EL drive circuit can be reduced and an organic EL display device using the same organic EL drive circuit.
2. Description of the Prior Art
It has been known that an organic EL display device, which realizes a high luminance display by light generated by itself, is suitable for a display on a small display screen and the organic EL display device has been attracting public attention as the next generation display device to be mounted on a portable telephone set, a DVD player or a PDA (Personal Digital Assistants) such as a portable terminal device, etc. Known problems of the organic EL display device are that, when it is driven by voltage as in a liquid crystal display device, luminance variation thereof becomes substantial and that, since there is difference in sensitivity between R (red), G (green) and B (blue), a control of luminance of a color display becomes difficult.
In view of these problems, an organic EL display device using current drive circuits has been proposed recently. For example, JPH10-112391A discloses a technique with which the luminance variation problem is solved by employing a current drive system.
An organic EL display panel of an organic EL display device for a portable telephone set, having 396 (132 3) terminal pins for column lines and 162 terminal pins for row lines has been proposed. However, there is a tendency that the number of column lines as well as row lines is further increased.
An output stage of a current drive circuit of such organic EL display panel of the active matrix type or the simple matrix type includes a current source drive circuit, such as an output circuit constructed with a current mirror circuit for each of the terminal pins. A drive stage thereof includes a parallel-driven type current mirror circuit (reference current distribution circuit) having a plurality of output side transistors for each of the terminal pins as disclosed in JP2002-82662 (domestic priority application claiming priorities of JP2001-86967 and JP2001-396219) corresponding to U.S. patent application Ser. No. 10,102,671. In the disclosed drive stage, a plurality of mirror currents are generated correspondingly to the respective terminal pins by branching a reference current from a reference current generator circuit to thereby drive the output circuits. Alternatively, the mirror currents distributed to the respective terminal pins are amplified by respective k-time current amplifier circuits, where k is an integer not smaller than 2, and the output circuits are driven with the amplified currents. The k-time amplifier circuit is disclosed in JP2002-33719, in which D/A converter circuits are provided correspondingly to the respective terminal pins and the D/A converter circuit converts display data corresponding to the column side terminal pins into analog data to generate column side drive currents simultaneously.
In a liquid crystal display device, the display luminance can be manually regulated by means of variable resistors, etc. Such luminance regulation of an organic EL panel is usually performed by generating a reference current corresponding to an external luminance regulation signal on the side of a reference current generator circuit. In the case of the current drive circuit having the above mentioned D/A converter circuit, however, it is possible to regulate luminance by arithmetically operating values of display data according to a luminance set.
When the luminance is to be doubled, the luminance regulation by the D/A converter circuit is performed by setting display data with which the display luminance data D becomes D 2 in the D/A converter circuit and, when the luminance is to be a half, it is performed by setting the display luminance data D ½ in the D/A converter circuit.
FIG. 3 shows a column driver 1 of an organic EL drive circuit capable of regulating luminance, which is disclosed in JP2002-33719. A D/A converter circuit and a current mirror type current output circuit are depicted by reference numerals 2 and 3, respectively.
The D/A converter circuit 2 includes a diode-connected input side NPN bipolar transistor Qa supplied at its collector with current I from a constant current-mirror-connected output side NPN bipolar transistors Qb to Qn−1 and N channel MOS FETs Trb to Trn−1 connected between emitters of the output side transistors Qb to Qn−1 and ground GND as switch circuits. Gates of the transistors Trb to Trn−1 are connected to respective input terminals of the D/A converter circuit to which display data D0 to Dn−1 are supplied.
The output side transistors Qb to Qn−1 have collectors connected to an output terminal 2b and have emitter area ratio corresponding to weights 1, 2, 4, n for respective digits, respectively. Incidentally, an emitter of the input side transistor Qa is grounded through a series circuit of a resistor Ra and an N channel MOS FET Tra and a gate of the transistor Tra is connected to a power source line +VDD.
The D/A converter circuit 2 converts digital display data corresponding to display luminance and supplied from a processor such as CPU or MPU, etc., to the input terminals D0 to Dn−1 thereof into analog currents corresponding to the input data (display data) and outputs the analog currents at the output terminal 2b. 
Incidentally, it should be noted that the output circuit of the reference current distribution circuit for each of the terminal pins of the drive stage is shown as the constant current source 14a. Further, transistors Trr and Qr constitute a base current supply circuit for supplying a base current to a common base line of the current-mirror-connection and an emitter of the transistor Qr is grounded through a series circuit of a resistor Rr and an N channel MOS FET Trra and a gate of the transistor Trra is connected to the power source line +VDD.
The current mirror type current output circuit 3 includes a drive stage current mirror circuit 3a and an output stage current mirror circuit 3b. 
The current mirror circuit 3a is a peak current generator circuit and constructed with an NPN type input side transistor Qs and an output side transistor Qt, which are diode-connected. Emitters of these transistors Qs and Qt are connected to an input terminal 3c of the output stage current mirror circuit 3b through a P channel MOS FET Trs and an N channel MOS FET Trt, respectively.
A collector of the input side transistor Qs is connected to the output terminal 2b of the D/A converter circuit 2 and a collector of the output side transistor Qt is grounded. An emitter area ratio of the transistor Qs to the transistor Qt is 1:x. Assuming that an output current of the D/A converter circuit 2 is Ia, a drive current generated at the input terminal 3c becomes (x+1) Ia. Therefore, the current mirror circuit 3a generates (1+x) times drive current when the transistor Trt is in ON state. The transistor Trs is a load transistor provided correspondingly to the transistor Trt and has a gate grounded to balance the drive line. The transistor Trt becomes ON for a constant time period in an initial drive period by a control signal CONT.
The current mirror circuit 3a drives an input side transistor Qx of the output stage current mirror circuit 3b through current mirror transistors Qu and Qw, which are provided for base current correction. As a result, current (1+x) Ia flows through the input side transistor Qx for a constant time during which the transistor Trt is turned ON. Thereafter, the drive current Ia is outputted as a normal drive current.
There is a recent tendency that the number of drive pins is increasing due to requested high resolution. Since the peak current generator circuit and the D/A converter circuit are provided correspondingly to each of terminal pins for current driving the organic EL elements, the size of integrated circuit is increasing. Therefore, in order to reduce power consumption and reduce the area occupied by the integrated circuit, which is increased with increase of the number of drive pins, it is important to reduce the size of these circuits.
However, if the luminance regulation is performed by the D/A converter circuit, the display data is operated by a processor such as CPU or MPU, etc., correspondingly to a set luminance and then set. In such case, the number of bits to be converted into an analog value becomes 6 or 7, so that the number of bits required exceeds an original number of bits of display data by 1 or 2, which is required for luminance regulation. Therefore, the area occupied by the D/A converter circuit is increased.
Aside from such luminance regulation, in a case where a high definition color display is performed or a tone range of display is increased for a case of monochromatic display, the number of bits to be converted by the D/A converter circuit becomes large. However, in the organic EL drive circuit having the D/A converter circuit shown in FIG. 3 and provided for each terminal pin of the organic EL display panel, an increase of the number of bits to be converted leads to an increase of area occupied by the D/A converter circuit. Therefore, an influence on the increase of the area occupied by the current drive circuit of the organic EL panel is larger than that of other circuits.